Today's integrated circuits include a vast number of devices. Smaller devices and shrinking ground rules are the key to enhance performance and to reduce cost. As FET (Field-Effect-Transistor) devices are being scaled down, the technology becomes more complex, and changes in device structures and new fabrication methods are needed to maintain the expected performance enhancement from one generation of devices to the next. The mainstay material of microelectronics is silicon (Si), or more broadly, Si based materials. Among others, one such Si based material of significance for microelectronics is the silicon-germanium (SiGe) alloy. The devices in the embodiments of the present disclosure are typically part of the art of single crystal, Si based material device technology.
There is a great difficulty in maintaining performance improvements in devices of deeply submicron generations. Therefore, methods for improving performance without scaling down have become of interest. There is a promising avenue toward higher gate dielectric capacitance without having to make the gate dielectric actually thinner. This approach involves the use of so called high-k materials. The dielectric constant of such materials is significantly higher than that of SiO2, which is about 3.9. A high-k material may physically be significantly thicker than oxide, and still have a lower equivalent oxide thickness (EOT) value. The EOT, a concept known in the art, refers to the thickness of such an SiO2 layer which has the same capacitance per unit area as the insulator layer in question. In today state of the art FET devices, one is aiming at an EOT of below 2 nm, and preferably below 1 nm.
Device performance is also enhanced by the use of metal gates. The depletion region in the poly-Si next to the gate insulator can become an obstacle in the path to increase gate-to-channel capacitance. The solution is to use a metal gate. Metal gates also assure good conductivity along the width direction of the devices, reducing the danger of possible RC delays in the gate.
Low power consumption small FET devices are in need of precise threshold voltage control. As operating voltage decreases, to below 2V, threshold voltages also have to decrease, and threshold variation becomes less tolerable. Every new element, such as a different gate dielectric, or a different gate material, influences the threshold voltage. Sometimes such influences are detrimental for achieving the desired threshold voltage values. Any technique which can affect the threshold voltage, without other effects on the devices is a useful one. Such techniques exist, for instance by using so called cap layers, or by exposing high-k gate dielectrics to oxygen.
Unfortunately, shifting the threshold of both PFET and NFET devices simultaneously, may not easily lead to threshold values in an acceptably tight range for CMOS circuits. There is need for a structure and a technique in which the threshold of one type of device can be independently adjusted without altering the threshold of the other type of device.
Typically, small FET devices with high-k dielectrics and metal gates require expensive complicated processing. It would be useful to find ways to simplify the fabrication process, while maintaining most of the performance offered by such advanced structures. At the same time it would also be desirable to adjust thresholds for low power operation. To date, such a structure, or fabrication process does not exists.